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HSP43168/883
TM
Data Sheet
May 1999
FN3177.3
Dual FIR Filter
The HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR cells each fed by a separate coefficient bank and one of two separate inputs. The outputs of the FIR cells are either summed or multiplexed by the MUX/Adder. The compute power in the FIR Cells can be configured to provide quadrature filtering, complex filtering, 2-D convolution, 1D/2-D correlations, and interpolating/decimating filters. The FIR cells take advantage of symmetry in FIR coefficients by pre-adding data samples prior to multiplication. This allows an 8-tap FIR to be implemented using only 4 multipliers per filter cell. These cells can be configured as either a single 16-tap FIR filter or dual 8-tap FIR filters. Asymmetric filtering is also supported. Decimation of up to 16 is provided to boost the effective number of filter taps from 2 to 16 times. Further, the Decimation Registers provide the delay necessary for fractional data conversion and 2-D filtering with kernels to 16 x 16. The flexibility of the dual is further enhanced by 32 sets of user programmable coefficients. Coefficient selection may be changed asynchronously from clock to clock. The ability to toggle between coefficient sets further simplifies applications such as polyphase or adaptive filtering. The HSP43168 is a low power fully static design implemented in an advanced CMOS process. The configuration of the device is controlled through a standard microprocessor interface.
Features
* This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR * 10-Bit Data and Coefficients * On-Board Storage for 32 Programmable Coefficient Sets * Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 20-Bit Data and Coefficients * Programmable Decimation to 16 * Programmable Rounding on Output * Standard Microprocessor Interface * 33MHz, 25.6MHz Versions
Applications
* Quadrature, Complex Filtering * Correlation * Image Processing * PolyPhase Filtering * Adaptive Filtering
Ordering Information
PART NUMBER HSP43168GM-25/883 HSP43168GM-33/883 TEMP. RANGE ( oC) -55 to 125 -55 to 125 PACKAGE 84 Ld PGA 84 Ld PGA PKG. NO. G84.A G84.A
Block Diagram
10 CIN0 - 9 A0 - 8 WR CSEL0 - 4 9 CONTROL / CONFIGURATION
COEFFICIENT BANK A 10 INA0 - 9 FIR CELL A MUX MUX
COEFFICIENT BANK B
FIR CELL B
INB0 - 9/ OUT0 - 8
10
MUX / ADDER 9 OEL OEH 19 OUT9 - 27
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
HSP43168/883 Pinouts
84 PIN PGA TOP VIEW
11 L GND OUT18 10 9 8 7 6 5 INB1 4 INB4 3 INB5 2 INB6 1 INB9 L
OUT15 OUT14 OUT12 OUT10 OUT11 OUT16 OUT13
K
VCC
VCC OUT9
INB0
INB2
GND
INB7
INB8
INA1
K
J
OUT19 OUT17
OEL
INB3
INA0
INA2
J
H
OUT21 OUT20
INA3
INA4
H
G F
OUT24 OUT23 OUT25 OUT27 OUT22 OUT26
INA7 INA8
INA5 INA9
INA6 VCC CIN0
G F
E
OEH
GND
CLK
CIN2
CIN1
E
D
VCC TXFR SHFT EN RVRS 11
ACCEN
GND
CIN3
D
C B
FWRD MUX0 MUX1 A0
A5 A3
A6 A2
CSEL0 VCC A8 5 CSEL2 CIN9
CIN6 CIN7
CIN4 CIN5
C B A PIN 'A1' ID
A
WR 10
GND 9
A1 8
A4 7
A7 6
CSEL1 CSEL3 CSEL4 CIN8 4 3 2 1
84 PIN PGA BOTTOM VIEW
11 A RVRS SHFT EN 10 WR 9 GND 8 A1 7 A4 6 A7 5 A8 4 3 2 1 A PIN 'A1' ID B
CSEL1 CSEL3 CSEL4 CIN8
B
MUX0 MUX1
A0
A3
A2
VCC CSEL0
CSEL2 CIN9
CIN7
CIN5
C
TXFR FWRD
A5
A6
CIN6
CIN4
C
D E
VCC OEH
ACCEN GND CLK CIN2
GND CIN1
CIN3 CIN0
D E
F
OUT27 OUT22 OUT26
INA8 INA7
INA9 INA5
VCC INA6
F G
G OUT24 OUT23 OUT25
H J
OUT21 OUT20 OUT19 OUT17 VCC OUT9 OEL INB3
INA3 INA0
INA4 INA2
H J
K
OUT18
OUT16 OUT13
VCC
INB0
INB2
GND
INB7
INB8
INA1
K
L
GND 11
OUT15 OUT14 OUT12 OUT10 OUT11 10 9 8 7 6
INB1 5
INB4 4
INB5 3
INB6 2
INB9 1
L
2
HSP43168/883 Pin Description
NAME VCC GND CIN0-9 A0-8 WR CSEL0-4 INA0-9 INB0-9 OUT9-27 PIN NUMBER B5, D11, K10, K7, F1 A9, E10, L11, K4, D2 E1-3, D1, C1-2, B1-3, A1 A5-8, B6-8, C6-7 A10 A2-4, B4, C5 K1, J1-2, H1-2, G1-3, F2-3 L1-5, K2-3, K5-6, J5 F9-11, G9-11, H10-11, J10-11, J7, K11, K8-9, L6-10 B11 C10 A11 C11 B9-10 E9 J6 E11 D10 I I I I I I/O O TYPE VCC: +5V power supply pin. Ground. Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB. Control/Coefficient Address Bus. Processor interface for addressing control and Coefficient Registers. A0 is the LSB. Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on the rising edge of WR. Coefficient Select. This input determines which of the 32 coefficient sets are to be used by FIR A and B. This input is registered and CSEL0 is the LSB. Input to FIR A. INA0 is the LSB. Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 is the LSB's of the output bus. 19 MSB's of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27 is the MSB. Shift Enable. This active low input enables shifting of data through the Decimation Registers. Forward ALU Input Enable. When active low, data from the forward decimation path is input to the ALU's through the "a" input. When high, the "a" inputs to the ALUs are zeroed. Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALU's through the "b" input. When high, the "b" inputs to the ALUs are zeroed. Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with the LIFO being written from the forward decimation path (see Figure 1). Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 3.0 lists the various configurations. Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables (OEL, OEH) are registered by the rising edge of CLK. Output Enable Low. This tristate control enables the LSB's of the output bus to INB1-9 when OEL is low. Output Enable High. This tristate control enables OUT9-27 when OEH is low. Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback path in the accumulator. DESCRIPTION
SHFTEN FWRD RVRS TXFR MUX0-1 CLK OEL OEH ACCEN
I I I I I I I I I
3
HSP43168/883
Absolute Maximum Ratings TA = 25oC
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . .300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC(oC/W) Ceramic PGA Package . . . . . . . . . . . . 33.5 7.5 Maximum Package Power Dissipation at 125oC Ceramic PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.49 W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to 125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32529 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS GROUP A SUB-GROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 2.2 3.0 2.6 -10 -10 MAX 0.8 0.8 0.4 +10 +10 500 UNITS V V V V V V A A A
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Logical One Input Voltage Clock Logical Zero Input Voltage Clock Output HIGH Voltage Output LOW Voltage Input Leakage Current Output Leakage Current Standby Power Supply Current Operating Power Supply Current Functional Test NOTES:
SYMBOL VIH VIL VIHC VILC VOH VOL II IO ICCSB
CONDITIONS VCC = 5.5V VCC = 4.5V VCC = 5.5V VCC = 4.5V IOH = -400A VCC= 4.5V (Note 1) IOL = +2.0mA VCC= 4.5V (Note 1) VIN = VCC or GND VCC = 5.5V VIN = VCC or GND VCC = 5.5V VIN = VCC or GND VCC = 5.5V, Outputs Open f = 25.6MHz, VIN = VCC or GND, VCC = 5.5V (Note 2) (Note 3)
ICCOP
1, 2, 3
-55 TA 125
-
281.6
mA
FT
7, 8
-55 TA 125
-
-
-
2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 11mA/MHz. 4. Tested as follows: f = 1MHz, VIH (clock inputs) = 3.4V, VIH (all other inputs) = 2.6V, V IL = 0.4V, VOH 1.5V, and VOL 1.5V.
4
HSP43168/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTE 5) CONDITIONS GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Note 7 Note 7 9, 10, 11 9, 10, 11 9, 10, 11 (-33MHz) TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 30 12 12 30 12 12 10 1 12 1.5 5 8 15 MAX (-25MHz) MIN 39 15 15 39 15 15 10 1 15 1.5 8 8 17 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER CLK Period CLK High CLK Low WR Period WR High WR Low Set-up Time; A0-8 to WR Low Hold Time; A0-8 to WR High Set-up Time; CIN0-9 to WR High Hold Time; CIN0-9 to WR High Set-up Time; WR Low to CLK Low Set-up Time; CIN0-9 to CLK Low Set-up Time; CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, MUX0-1 to CLK High Hold Time; CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, MUX0-1 to CLK High CLK to Output Delay OUT0-27 Output Enable Time NOTES:
SYMBOL TCP TCH TCL TWP TWH TWL TAWS TAWH TCWS TCWH TWLCL TCVCL TECS
TECH
9, 10, 11
-55 TA 125
0
-
0
-
ns
TDO TOE Note 6
9, 10, 11 9, 10, 11
-55 TA 125 -55 TA 125
-
15 12
-
17 12
ns ns
5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 3.0V and 0V; timing reference levels (CLK) 2.0V; all others 1.5V. VCC = 4.5V and 5.5V. Output load per test load circuit with CL = 40 pF. Output transition is measured at VOH S > 1.5V and V OL < 1.5V. 6. Transition is measured at 200mV from steady state voltage, Output loading per test load circuit, CL = 40pF. 7. Set-up time requirements for loading of data on CIN0-9 to guarantee recognition on the following clock.
5
HSP43168/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (-33MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT CONDITIONS VCC = Open, f = 1 MHz, All measurements are referenced to device GND. NOTES 1 1 TEMPERATURE (oC) TA = 25 TA = 25 -55 TA 125 -55 TA 125 -55 TA 125 MIN MAX 12 12 (-25MHz) MIN MAX 12 12 UNITS pF pF
Output Disable Time Output Rise Time Output Fall Time NOTES:
TOD tR tF From 0.8V to 2.0V From 2.0V to 0.8V
1, 2 1, 2 1, 2
-
12 8 8
-
12 8 8
ns ns ns
8. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 9. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
AC Test Load Circuit
S1 DUT *CL
IOH * INCLUDES STRAY AND JIG CAPACITANCE
1.5V
IOL
EQUIVALENT CIRCUIT SWITCH S1 OPEN FOR ICCSB AND ICCOP TEST
6
HSP43168/883 Waveforms
tCP tCH CLK tCL
tECS CSEL0-4, MUX0-1 SHFTEN, FWRD, RVRS, TXFR, INA0-9, INB0-9 tDO OUT0-27
tECH
tWLCL tWP tWL WR tWH
tAWS A0-8
tAWH
tCWS CIN0-15
tCWH
tCVCL 1.5V 1.5V
OEL, OEH
tOE 1.7V OUT0-27 HIGH IMPEDANCE 1.3V
tOD
HIGH IMPEDANCE
OUTPUT ENABLE, DISABLE TIMING
2.0V 0.8V
2.0V 0.8V
tRF
tRF
OUTPUT RISE AND FALL TIMES
7
HSP43168/883 Burn-In Circuit
84 PIN PGA BOTTOM VIEW
11 A B C D E RVRS 10 WR 9 GND 8 A1 A0 7 A4 A3 A5 6 A7 A2 A6 5 A8 VCC CSEL0 4 3 2 1 A B C D E PIN 'A1' ID
CSEL1 CSEL3 CSEL4 CIN8 CSEL2 CIN9 CIN7 CIN6 GND CIN5 CIN4 CIN3 CIN0
SHFT MUX0 MUX1 EN TXFR FWRD VCC OEH ACCEN GND CLK
CIN2
CIN1
F G
OUT27 OUT22 OUT26 OUT24 OUT23 OUT25
INA8 INA7
INA9 INA5
VCC INA6
F G
H J K
OUT21 OUT20 OUT19 OUT17 OUT18 VCC OUT9 OUT16 OUT13 VCC OEL INB0 INB3 INB2 GND INB7
INA3 INA0 INB8
INA4 INA2 INA1
H J K
L
GND OUT15 OUT14 OUT12 OUT10 OUT11 INB1 11 10 9 8 7 6 5
INB4 4
INB5 3
INB6 2
INB9 1
L
NOTES: 1. VCC/2 (2.7V 10%) used for outputs only. 2. 47K (20%) resistor connected to all pins except VCC and GND. 3. V CC = 5.5 0.5V. 4. 0.1f (Min) capacitor between VCC and GND per position. 5. F0 = 100KHz 10%, F1 = F0/2, F2 = F1/2. . . , F16 = F15/2, 40 to 60% duty cycle. 6. Input voltage limits: VIL = 0.8V Max, VIH = 4.5 10%.
8
HSP43168/883
PGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 E11 F1 F2 F3 PIN NAME CIN8 CSEL4 CSEL3 CSEL1 A8 A7 A4 A1 GND WRB RVRS CIN5 CIN7 CIN9 CSEL2 VCC A2 A3 A0 MUX1 MUX0 SHFTEN CIN4 CIN6 CSEL0 A6 A5 FWRD TXFR CIN3 GND ACCEN VCC CIN0 CIN1 CIN2 CLK GND OEHB VCC INA9 INA8 BURN-IN SIGNAL F9 F12 F11 F9 F12 F10 F11 F12 GND F6 F12 F8 F10 F10 F10 VCC F11 F10 F13 F13 F12 F14 F7 F9 F8 F11 F12 F13 F11 F10 GND F13 VCC F7 F8 F9 F0 GND F14 VCC F10 F9 F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 J1 J2 J5 J6 J7 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10
L11
PGA PIN
PIN NAME SUM26 SUM22 SUM27 INA6 INA5 INA7 SUM25 SUM23 SUM24 INA4 INA3 SUM20 SUM21 INA2 INA0 INB3 OELB SUM9 SUM17 SUM19 INA1 INB8 INB7 GND INB2 INB0 VCC SUM13 SUM16 VCC SUM18 INB9 INB6 INB5 INB4 INB1 SUM11 SUM10 SUM12 SUM14 SUM15
GND
BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 F7 F6 F8 VCC/2 VCC/2 VCC/2 F5 F4 VCC/2 VCC/2 F3 F1 F4 F13 VCC/2 VCC/2 VCC/2 F2 F9 F8 GND F3 F1 VCC VCC/2 VCC/2 VCC VCC/2 F10 F7 F6 F5 F2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
GND
9
HSP43168/883 Die Characteristics
DIE DIMENSIONS: 314 x 348 x 19 1mils METALLIZATION: Type: Si-Al or Si-Al-Cu Thickness: 8kA GLASSIVATION: Type: Nitrox Thickness: 10kA WORST CASE CURRENT DENSITY: 1.93 x 105 A/cm2
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